A triple-well structure in a semiconductor device generally includes a “shallow P well” (high-voltage P well) and a “shallow N well” (high-voltage N well) formed in a P-type silicon substrate, and a “deep N well” that is formed under the shallow P well and is electrically connected to the shallow N well (as in, for example, Japanese Patent Application JP H11-261022 A).
A semiconductor device having a triple-well structure generally is formed by the following manufacturing process. Element isolation is performed by a shallow trench isolation (STI) technique or the like between an N-type transistor formation area and a P-type transistor formation area in a P-type silicon substrate. Next, a half part of the element isolation film located on the P-type transistor formation area side is covered with a resist mask, and boron ions, for example, are implanted at a part of the surface layer of the N-type transistor formation area, thus forming a shallow P well. Subsequently, phosphorous ions, for example, are implanted through the P well using the same resist mask at a part under the P well, thus forming a deep N well. After removing the resist mask, a half part of the element isolation film located on the N-type transistor formation area side is covered with a resist mask, and phosphorus ions, for example, are implanted at a part of the surface layer of the P-type transistor formation area, thus forming a shallow N well. The deep N well and the shallow N well are thereby electrically connected, and the shallow P well and the P-type silicon substrate are insulated electrically. In this way, a triple-well structure formed by this manufacturing process includes an element isolation film that extends over the boundary between the shallow P well and the shallow N well.
However, this triple-well structure may have difficulty in lowering the resistance at the connection part of the “shallow N well” and the “deep N well,” and tends to generate latchup due to a parasitic transistor generated by the manufacturing process.